Name
Abstract | ||
|---|---|---|
The complexity of System-on-Chip (SoC) designs continues to grow as each SoC features an increasing variety of loosely coupled accelerators together with multiple processor cores. Specialized-hardware accelerators are typically designed in isolation, optimized for the algorithm they are implementing, and with limited consideration of the implications of their integration into a given SoC. However,... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/MM.2018.2877288 | IEEE Micro |
Keywords | Field | DocType |
Sockets,Protocols,Software,Coherence,Memory management,Registers,Hardware acceleration | Memory hierarchy,Computer science,Parallel computing,Coherence (physics),Multi-core processor | Journal |
Volume | Issue | ISSN |
38 | 6 | 0272-1732 |
Citations | PageRank | References |
5 | 0.42 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Davide Giri | 1 | 16 | 4.18 |
| Paolo Mantovani | 2 | 106 | 10.58 |
| Luca P. Carloni | 3 | 1713 | 120.17 |