Paolo Mantovani - Citegraph

Author Info

Name	Affiliation	Papers
PAOLO MANTOVANI	Politecnico di Torino, Torino, Italy	23
Collaborators	Citations	PageRank
28	106	10.58
Referers	Referees	References
274	892	366

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100892

Publications (23 rows)

Collaborators (28 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs	3	0.39	2021
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis	0	0.34	2020
Agile SoC Development with Open ESP - Invited Paper.	0	0.34	2020
Teaching Heterogeneous Computing with System-Level Design Methods	0	0.34	2019
Runtime reconfigurable memory hierarchy in embedded scalable platforms.	0	0.34	2019
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs	0	0.34	2019
Accelerators and Coherence: An SoC Perspective.	5	0.42	2018
NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators	1	0.36	2018
System-level design of networks-on-chip for heterogeneous systems-on-chip	1	0.36	2017
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.	9	0.58	2017
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip	3	0.38	2017
Broadening the exploration of the accelerator design space in embedded scalable platforms	3	0.38	2017
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip	2	0.38	2016
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.	6	0.48	2016
High-level synthesis of accelerators in embedded scalable platforms	9	0.55	2016
Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration	2	0.37	2016
On the design of scalable and reusable accelerators for big data applications.	3	0.38	2016
An analysis of accelerator coupling in heterogeneous architectures	26	0.79	2015
A synchronous latency-insensitive RISC for better than worst-case design.	2	0.36	2015
Accelerator Memory Reuse in the Dark Silicon Era	15	0.68	2014
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI.	14	1.29	2012
Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study	0	0.34	2011
On maximal intermediate predicate constructive logics	2	0.41	1996