Name
Title | ||
|---|---|---|
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. |
Abstract | ||
|---|---|---|
This paper proposes a time-to-digital converter (TDC) that achieves wide input range and fine time resolution at the same time. The proposed TDC utilizes pulse-shrinking (PS) scheme in the second stage for a fine resolution and two-step (TS) architecture for a wide range. The proposed PS TDC prevents an undesirable nonuniform shrinking rate issue in the conventional PS TDCs by utilizing a built-in... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TVLSI.2018.2867505 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Delays,Signal resolution,Jitter,Very large scale integration,Calibration,Transistors | Computer science,16-bit,Electronic engineering,CMOS,Jitter,Transistor,Very-large-scale integration,Calibration,Offset (computer science),Radio propagation | Journal |
Volume | Issue | ISSN |
27 | 1 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ryuichi Enomoto | 1 | 0 | 0.34 |
| Tetsuya Iizuka | 2 | 92 | 33.22 |
| Takehisa Koga | 3 | 1 | 0.72 |
| Toru Nakura | 4 | 92 | 31.27 |
| kunihiro asada | 5 | 273 | 78.26 |