Paper Info
Title
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications
Abstract
Automotive has become one of the most prevailing sectors of the modern semiconductor industry. Due to strict requirements for safety, reliability, and security the proposed test & repair solutions for automotive applications undergo a circumstantial verification before exploitation. Traditionally production defects and soft errors occurring in the operation mode were considered to be the main source of failures for System-on-Chips (SoC). Nevertheless, aging-induced faults especially in modern technology nodes also pose certain challenges for SoC lifetime and impact the overall Failure in Time (FIT) rate of the system. Meanwhile keeping hold of low FIT rate is one of the main criteria for reliability. In this paper, a comprehensive study on aging faults is conducted for FinFET memories and an efficient test & repair methodology is proposed that meets the automotive requirements and allows decreasing the FIT rate of the system.
Year
DOI
Venue
2018
10.1109/TEST.2018.8624890
2018 IEEE International Test Conference (ITC)
Keywords
Field
DocType
system-on-chips,failure in time rate,SoC lifetime,automotive requirements,FinFET memories,aging faults,low FIT rate,modern technology nodes,aging-induced faults,operation mode,soft errors,production defects,circumstantial verification,automotive applications,test & repair solutions,strict requirements,modern semiconductor industry
Computer science,Operation mode,Electronic engineering,Semiconductor industry,Reliability engineering,Automotive industry
Conference
ISSN
ISBN
Citations 
1089-3539
978-1-5386-8383-5
1
PageRank 
References 
Authors
0.37
0
7
Name
Order
Citations
PageRank
G. Tshagharyan182.29
Gurgen Harutyunyan2197.30
Yervant Zorian31994215.23
Anteneh Gebregiorgis4224.91
Mohammad Saber Golanbari5236.43
Rajendra Bishnoi613219.64
Mehdi B. Tahoori71537163.44