Gurgen Harutyunyan - Citegraph

Author Info

Name	Affiliation	Papers
GURGEN HARUTYUNYAN	Synopsys, Inc., Yerevan, Armenia	18
Collaborators	Citations	PageRank
41	19	7.30
Referers	Referees	References
61	164	57

Search Limit

100164

Publications (18 rows)

Collaborators (41 rows)

Referers (61 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications	0	0.34	2020
Test and Diagnosis Solution for Functional Safety	1	0.43	2020
Memory Physical Aware Multi-Level Fault Diagnosis Flow	2	0.42	2020
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism	0	0.34	2019
Innovative Practices on In-System Test and Reliability of Memories	0	0.34	2019
Memory FIT Rate Mitigation Technique for Automotive SoCs	0	0.34	2019
Case Study and Advanced Functional Safety Solution for Automotive SoCs	0	0.34	2018
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications	1	0.37	2018
Advanced Uniformed Test Approach For Automotive SoCs	1	0.63	2018
Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs	1	0.41	2018
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM	5	0.45	2018
An efficient testing methodology for embedded flash memories.	0	0.34	2017
Experimental study on Hamming and Hsiao codes in the context of embedded applications.	1	0.43	2017
Automated flow for test pattern creation for IPs in SoC.	0	0.34	2017
A power based memory BIST grouping methodology	0	0.34	2015
Overview study on fault modeling and test methodology development for FinFET-based memories	1	0.36	2015
Extending fault periodicity table for testing faults in memories under 20nm	2	0.43	2014
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs	4	0.66	2012

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