Title
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI.
Abstract
Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1800 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{\mathbf {2}}$ </tex-math></inline-formula> .
Year
DOI
Venue
2019
10.1109/JSSC.2018.2881923
J. Solid-State Circuits
Keywords
Field
DocType
Transistors,Stress,Integrated circuits,Human computer interaction,Aging,Stress measurement,Phase measurement
Temperature instability,NMOS logic,Computer science,Massively parallel,Chip,Electronic engineering,CMOS,PMOS logic,Transistor,Integrated circuit
Journal
Volume
Issue
ISSN
54
2
0018-9200
Citations 
PageRank 
References 
2
0.58
0
Authors
10