Name
Abstract | ||
|---|---|---|
Resistive RAM (RRAM) is one of the emerging non-volatile memories that may not only replace DRAM and/or Flash in the future, but also enable new computing paradigms such as computation-in-memory. Providing high quality and efficient test solutions are of great importance in order to enable the commercialization of such products. This paper discusses all aspects of RRAM testing including defects, fault models, test algorithms, Design-for-Testability (DFT) schemes, and future challenges. The paper highlights also the limitations and the inaccuracies of existing approaches and shows that using a linear resistor to model a defect in RRAM (as it is done today) is too pessimistic, and unable to represent the non-linear behavior of the defective RRAM devices. This may result in incorrect fault models, which in turn leads to low quality test solutions. The paper therefore also presents a novel defect modeling methodology that appropriately captures the non-linear RRAM behavior. To show its superiority, the methodology is applied to a forming defect and the results are compared with those of traditional approach. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TEST.2018.8624895 | 2018 IEEE International Test Conference (ITC) |
Keywords | Field | DocType |
RRAM,Test,DFT,Defect Model,Defect | Dram,Test algorithm,Computer science,Resistive touchscreen,Electronic engineering,Resistor,Commercialization,Resistive random-access memory | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-5386-8383-5 | 2 |
PageRank | References | Authors |
0.37 | 16 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Moritz Fieback | 1 | 8 | 3.03 |
| Mottaqiallah Taouil | 2 | 224 | 33.40 |
| Said Hamdioui | 3 | 887 | 118.69 |