| Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron | 0 | 0.34 | 2021 |
| Evaluation Of Single Event Upset Susceptibility Of Finfet-Based Srams With Weak Resistive Defects | 0 | 0.34 | 2021 |
| Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks | 0 | 0.34 | 2021 |
| Applying Thermal Side-Channel Attacks on Asymmetric Cryptography | 1 | 0.38 | 2021 |
| Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs | 1 | 0.43 | 2021 |
| Hard-to-Detect Fault Analysis in FinFET SRAMs | 0 | 0.34 | 2021 |
| Protecting IoT Devices through a Hardware-driven Memory Verification | 0 | 0.34 | 2021 |
| Skeleton-based Synthesis Flow for Computation-In-Memory Architectures | 0 | 0.34 | 2020 |
| A Security Verification Template to Assess Cache Architecture Vulnerabilities | 0 | 0.34 | 2020 |
| RNN-Based Detection of Fault Attacks on RSA | 0 | 0.34 | 2020 |
| LiD-CAT: A Lightweight Detector for Cache ATtacks | 0 | 0.34 | 2020 |
| eSRAM Reliability: Why is it still not optimally solved? | 0 | 0.34 | 2020 |
| The Power of Computation-in-Memory Based on Memristive Devices | 1 | 0.35 | 2020 |
| Modeling Static Noise Margin for FinFET based SRAM PUFs | 0 | 0.34 | 2020 |
| Testing Scouting Logic-Based Computation-in-Memory Architectures | 2 | 0.38 | 2020 |
| Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects | 0 | 0.34 | 2020 |
| A Classification of Memory-Centric Computing | 3 | 0.37 | 2020 |
| RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems | 0 | 0.34 | 2020 |
| Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs | 2 | 0.37 | 2020 |
| G-PUF: An Intrinsic PUF Based on GPU Error Signatures | 0 | 0.34 | 2020 |
| Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level | 2 | 0.50 | 2020 |
| S-NET - A Confusion Based Countermeasure Against Power Attacks for SBOX. | 0 | 0.34 | 2020 |
| Testing Computation-in-Memory Architectures Based on Emerging Memories | 1 | 0.36 | 2019 |
| Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM | 1 | 0.37 | 2019 |
| A computation-in-memory accelerator based on resistive devices | 2 | 0.36 | 2019 |
| System-Level Sub-20 Nm Planar And Finfet Cmos Delay Modelling For Supply And Threshold Voltage Scaling Under Process Variation | 0 | 0.34 | 2019 |
| Hardware-Based Aging Mitigation Scheme for Memory Address Decoder | 0 | 0.34 | 2019 |
| Methodology for Application-Dependent Degradation Analysis of Memory Timing | 1 | 0.37 | 2019 |
| Challenges and Solutions in Emerging Memory Testing | 7 | 0.52 | 2019 |
| Software-Based Mitigation for Memory Address Decoder Aging | 0 | 0.34 | 2019 |
| Time-Division Multiplexing Automata Processor | 0 | 0.34 | 2019 |
| Applications of Computation-In-Memory Architectures based on Memristive Devices | 3 | 0.40 | 2019 |
| Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing | 0 | 0.34 | 2019 |
| DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs | 1 | 0.39 | 2019 |
| Reliability Modeling and Mitigation for Embedded Memories | 0 | 0.34 | 2019 |
| Device-Aware Test: A New Test Approach Towards DPPB Level | 2 | 0.37 | 2019 |
| Energy Optimization For Large-Scale 3d Manycores In The Dark-Silicon Era | 0 | 0.34 | 2019 |
| Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme | 0 | 0.34 | 2019 |
| Memory and Communication Profiling for Accelerator-Based Platforms. | 0 | 0.34 | 2018 |
| Impact and mitigation of SRAM read path aging. | 0 | 0.34 | 2018 |
| Ionizing radiation modeling in DRAM transistors | 0 | 0.34 | 2018 |
| A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs. | 1 | 0.38 | 2018 |
| Memristive Devices For Computation-In-Memory | 0 | 0.34 | 2018 |
| Testing Resistive Memories: Where are We and What is Missing? | 2 | 0.37 | 2018 |
| Electrical Modeling of STT-MRAM Defects | 7 | 0.47 | 2018 |
| A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar. | 4 | 0.48 | 2018 |
| Degradation analysis of high performance 14nm FinFET SRAM | 1 | 0.37 | 2018 |
| Interconnect networks for resistive computing architectures | 0 | 0.34 | 2017 |
| Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier. | 7 | 0.62 | 2017 |
| On the Implementation of Computation-in-Memory Parallel Adder. | 4 | 0.39 | 2017 |
