Name
Title | ||
|---|---|---|
A 0.015-mm $^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology |
Abstract | ||
|---|---|---|
This brief illustrates the design of an inductorless high-speed clock generator. Compared to inductance-capacitance (LC) oscillators, ring oscillators are used in order to achieve a wide frequency-tuning range with a small chip area. By employing a cascaded phase-locked loop (PLL) architecture, the phase noise of the oscillator can be effectively suppressed. The first PLL is implemented with high-... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCSII.2015.2504274 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Clocks,Phase locked loops,Tuning,Voltage-controlled oscillators,Ring oscillators,Phase noise | Journal | 64 |
Issue | ISSN | Citations |
6 | 1549-7747 | 2 |
PageRank | References | Authors |
0.47 | 2 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gyu-Seob Jeong | 1 | 21 | 9.00 |
| Wooseok Kim | 2 | 29 | 5.64 |
| Jaejin Park | 3 | 70 | 8.49 |
| Taeik Kim | 4 | 2 | 1.48 |
| Ho-Jin Park | 5 | 36 | 6.77 |
| Deog-Kyoon Jeong | 6 | 16 | 10.57 |