Name
Abstract | ||
|---|---|---|
An SMT(Simultaneous MultiThreading) architecture processor aims to progress processor performance by executing parallel threads. However, the increasing cache misses caused by the capacity miss and the conflict miss in the shared cache memory. In this paper, we propose a thread scheduler based on a concept of thread affinity. Our proposed system observes performance of concerning threads with common cache and reschedules them. In addition, we have developed a strategy to choose the suitable thread number according to decreasing of cache hit ratio. As experimental results, the system with our thread scheduler performs up to 1.96 times higher with benchmark programs of RADIX sort in SPLASH-2. |
Year | Venue | Keywords |
|---|---|---|
2005 | PDPTA '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS 1-3 | thread scheduler, multithreaded architecture, system software |
Field | DocType | Citations |
System software,Cellular architecture,Win32 Thread Information Block,Computer architecture,Scheduler activations,Scheduling (computing),Computer science,Parallel computing,Thread (computing),Microarchitecture | Conference | 1 |
PageRank | References | Authors |
0.40 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaname Uchikura | 1 | 5 | 1.95 |
| Koichi Sasada | 2 | 9 | 2.50 |
| Mikiko Sato | 3 | 22 | 11.53 |
| Masanori Yamato | 4 | 3 | 1.19 |
| Norito Kato | 5 | 3 | 1.19 |
| Hironori Nakajo | 6 | 69 | 20.66 |
| Mitaro Namiki | 7 | 97 | 20.69 |