Name
Abstract | ||
|---|---|---|
The demand for energy-efficient I/O link transceivers operating at raw data-rates in the tens of Gb/s continues to fuel innovation in the field of wireline communication [1]. Receiving equalizers under one pJ/b are sought for chip-to-chip and chip-to-module links designed to operate across short-reach copper channels. Standards such as CEI-28G-VSR suit chip-to-module communication at raw data rates up to 28Gb/s and 10–12dB insertion loss at Nyquist. Proprietary and open standards in the same speed range are being developed too for data and memory-centric systems co-designed with CPUs and GPUs and channels with insertion loss on the order of 20dB [2]. |
Year | Venue | Field |
|---|---|---|
2016 | ISSCC | Wireline,Transceiver,Computer science,Communication channel,Raw data,Electronic engineering,CMOS,Bandwidth (signal processing),Nyquist–Shannon sampling theorem,Insertion loss,Electrical engineering |
DocType | Citations | PageRank |
Conference | 2 | 0.43 |
References | Authors | |
3 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pier Andrea Francese | 1 | 138 | 25.33 |
| Matthias Braendli | 2 | 158 | 24.28 |
| Christian Menolfi | 3 | 245 | 41.54 |
| Marcel A. Kossel | 4 | 179 | 33.86 |
| Thomas Morf | 5 | 244 | 42.54 |
| Lukas Kull | 6 | 141 | 18.63 |
| Alessandro Cevrero | 7 | 107 | 16.21 |
| Hazar Yueksel | 8 | 7 | 4.15 |
| Ilter Oezkaya | 9 | 2 | 1.10 |
| Danny Luu | 10 | 16 | 7.55 |
| Thomas Toifl | 11 | 275 | 48.02 |