Name
Abstract | ||
|---|---|---|
The effectiveness of cache-based memory hierarchies depends on the presence of spatial and temporal locality in applications. Memory accesses of many important applications have predictable behavior but poor locality. As a result, the performance of these applications suffers from the increasing gap between processor and memory performance. In this paper, we describe a novel mechanism provided by the Impulse memory controller called Dynamic Cache Line Assembly that can be used by applications to improve memory performance. This mechanism allows applications to gather on-the-fly data spread through memory into contiguous cache lines, which creates spatial data locality where none exists naturally. We have used dynamic cache line assembly to optimize a random access loop and an implementation of Fast Fourier Transform (FFTW). Detailed simulation results show that the use of dynamic cache line assembly improves the performance of these benchmarks by up to a factor of 3.2 and 1.4, respectively. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1007/3-540-44570-6_4 | Intelligent Memory Systems |
Keywords | Field | DocType |
contiguous cache line,impulse memory controller,dynamic cache line assembly,novel mechanism,cache-based memory hierarchy,temporal locality,memory system support,memory access,poor locality,memory performance,on-the-fly data,random access,fast fourier transform,spatial data | Locality of reference,Cache pollution,Cache,Computer science,Parallel computing,Cache-only memory architecture,Page cache,Cache algorithms,Non-uniform memory access,Cache coloring | Conference |
ISBN | Citations | PageRank |
3-540-42328-1 | 4 | 0.42 |
References | Authors | |
7 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lixin Zhang | 1 | 571 | 45.96 |
| Venkata K. Pingali | 2 | 129 | 12.68 |
| Bharat Chandramouli | 3 | 11 | 1.30 |
| John B. Carter | 4 | 1785 | 162.82 |