Paper Info
Title
A passive equalizer and its design methodology for global interconnects in VLSIs
Abstract
The deterioration of signal integrity (SI) due to the skin effect and dielectric loss has been one of the most serious problems in the printed circuit board (PCB) trace since the clock frequency exceeded several hundred MHz. It is expected that the same problem will occur due to the same causes when the frequency exceeds several GHz in global and very long interconnects in very-large-scale integration (VLSI) and in silicon interposers. Currently, in PCBs, this problem is typically overcome by using either passive equalizers based on lumped-element circuits or active equalizers. Unfortunately, however, those equalizers are not suitable for VLSI interconnects in terms of power consumption and parasitic elements. In this paper, we apply a passive equalizer based on distributed-element circuits to global interconnects in VLSIs and silicon interposers; furthermore, we propose a design methodology for this. We fabricate a scale-up prototype of the proposed equalizer and demonstrate that the SI is improved; compared with a conventional interconnect, the jitter is reduced by 55.5%, and the eye height is increased by 75%.
Year
DOI
Venue
2016
10.1109/VLSI-SoC.2016.7753552
2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Keywords
Field
DocType
passive equalizer,global interconnects,VLSI,distributed-element circuits,silicon interposers
Signal integrity,Printed circuit board,Electronic engineering,Interposer,Engineering,Jitter,Interconnection,Electronic circuit,Electrical engineering,Very-large-scale integration,Clock rate
Conference
ISBN
Citations 
PageRank 
978-1-5090-3562-5
0
0.34
References 
Authors
0
3
Name
Order
Citations
PageRank
Moritoshi Yasunaga117833.03
Naoki Yokoshima200.68
Ikuo Yoshihara312018.53