Title
4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing
Abstract
High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1-4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1-3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.
Year
DOI
Venue
2017
10.1109/ISSCC.2017.7870271
2017 IEEE International Solid-State Circuits Conference (ISSCC)
Keywords
Field
DocType
high-speed vision chip,3D-stacked column-parallel PE,spatio-temporal image processing,high-speed vision systems,high-frame-rate imaging,highly-parallel signal processing,instantaneous visual feedback,human-visual-recognition speed,high-frame-rate processing,matrix-based processing element parallelization,time 1 ms
Signal processing,Machine vision,High speed vision,Matrix (mathematics),Computer science,Image processing,Electronic engineering,Computational science,Artificial intelligence,Computer vision,Object detection,Chip,SIMPLE algorithm
Conference
ISBN
Citations 
PageRank 
978-1-5090-3759-9
6
0.66
References 
Authors
3
15