Name
Title | ||
|---|---|---|
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. |
Abstract | ||
|---|---|---|
For wireline transmitters delivering a high-speed multi-level signal, such as pulse-amplitude-modulation-4 or duobinary, a high-performance multiplexer (MUX) is critical to serialize the low-speed parallel data into one full-speed output. To enhance the power efficiency and data eye's opening, this paper proposes a universal 2-to-1 MUX, featuring a cross-quadrature clocking technique to enlarge th... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCSI.2018.2829725 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Clocks,Delays,Transmitters,Latches,Data centers,Multiplexing | Electrical efficiency,Transmitter,Timing margin,CMOS,Electronic engineering,Multiplexer,Bandwidth (signal processing),Jitter,Multiplexing,Mathematics | Journal |
Volume | Issue | ISSN |
65 | 9 | 1549-8328 |
Citations | PageRank | References |
3 | 0.42 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong Chen | 1 | 36 | 8.00 |
| Peng Un Mak | 2 | 301 | 65.06 |
| Chirn Chye Boon | 3 | 136 | 26.81 |
| Rui Paulo da Silva Martins | 4 | 642 | 127.35 |