Title
Impact of Passive & Active Load Gate Impedance on Breakdown Hardness in 28nm FDSOI Technology
Abstract
The impact of integrated gate impedances, passive (polycomb, R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> ) and active (Input/Output MOSfet, Z <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">load</inf> ), on the breakdown (BD) behaviors of 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) transistors is discussed. It has been shown that R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> and Z <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">load</inf> affect directly the BD hardness of the devices. By reducing the BD hardness, a catastrophic failure of gate dielectric meaning complete loss of device functionalities can be avoided. Many configurations of R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> , Z <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">load</inf> are considered to obtain the best compromise in terms the BD hardness and functionalities of Device Under Test (DUT).
Year
DOI
Venue
2019
10.1109/IRPS.2019.8720591
2019 IEEE International Reliability Physics Symposium (IRPS)
Keywords
Field
DocType
CMOS,Breakdown Hardness,FDSOI,TDDB,Reliability
Engineering physics,Active load,Electrical impedance,Electronic engineering,Engineering
Conference
ISSN
ISBN
Citations 
1541-7026
978-1-5386-9504-3
0
PageRank 
References 
Authors
0.34
0
7
Name
Order
Citations
PageRank
A.P. Nguyen100.34
X. Garros273.00
M. Rafik352.13
Florian Cacho4147.99
D. Roy5105.32
X. Federspiel654.42
F. Gaillard700.68