Name
Title | ||
|---|---|---|
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. |
Abstract | ||
|---|---|---|
This article analyzes the jitter-power tradeoff in multiplying delay-locked loops (MDLLs), which differs from the more typical phase-locked loop one, and identifies a design optimization criterion. The methodology is applied to a fractional-
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula>
MDLL with a sub-sampling bang-bang phase detector and a novel digital-to-time converter (DTC) range-reduction technique, which limits the jitter added to the reference signal, at no additional power penalty. The prototype has been implemented in 65-nm CMOS and covers a 1.6-to-3.0-GHz tuning range, achieving an absolute rms jitter (integrated from 30 kHz to 30 MHz) of 397 fs at 2.5-mW power, with a corresponding jitter-power figure of merit of −244 dB. In-band fractional spurs are as low as −51.5 dB and the occupied core area is 0.0275 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/CICC.2019.8780235 | IEEE Journal of Solid-state Circuits |
Keywords | DocType | Volume |
Jitter,Phase locked loops,Bandwidth,Phase noise,Multiplexing,Optimization | Journal | 54 |
Issue | ISSN | ISBN |
11 | 0018-9200 | 978-1-5386-9396-4 |
Citations | PageRank | References |
7 | 0.46 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alessio Santiccioli | 1 | 17 | 3.01 |
| Mario Mercandelli | 2 | 15 | 4.32 |
| Andrea L. Lacaita | 3 | 320 | 42.41 |
| Carlo Samori | 4 | 349 | 39.76 |
| Salvatore Levantino | 5 | 351 | 43.23 |