Name
Title | ||
|---|---|---|
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration |
Abstract | ||
|---|---|---|
A pipeline analog-to-digital converter (ADC) with high power efficiency is implemented in this paper. The ADC architecture consists of 3.5b, 3.5b, 3.5b, and 4b sub-ADCs. For the first three stages, a current-reuse technique is employed in the current mode multiplying digital-to-analog converters (MDACs). An operational transconductance amplifier (OTA) converts an input voltage into current; A current-steering DAC reuses the OTA bias current. The OTA and the DAC generate the sub-ADC residue in a current domain. As a result, both power consumption and thermal noise for the MDAC are reduced. A transimpedance amplifier (TIA) with a feedback resistor is utilized to convert the current signal to a voltage residue signal for the next stage. An off-chip calibration scheme is used to correct interstage gain and nonlinearity errors. The fabricated ADC achieves 68.1 dB signal-to-noise-and-distortion ratio (SNDR) and 82.3 dB spurious free dynamic range (SFDR) for a sinusoidal input at 4.17 MHz. The ADC operates at a maximum sampling frequency of 260 MHz. With an input signal at 123.129 MHz, the measured SNDR/SFDR are 66.3/78.22 dB, respectively. The total power consumption for the ADC running at maximum speed is 15.38 mW. Thus, the pipeline ADC achieves a 167.4 dB figure-of-merit (FoM). The chip was manufactured in a TSMC 40-nm CMOS process. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCSI.2019.2925743 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Pipelines,Computer architecture,Calibration,Resistors,Transconductance,Gain,Power demand | Electrical efficiency,Operational transconductance amplifier,Sampling (signal processing),Noise (electronics),Spurious-free dynamic range,Electronic engineering,Transimpedance amplifier,Resistor,Transconductance,Mathematics | Journal |
Volume | Issue | ISSN |
66 | 9 | 1549-8328 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dadian Zhou | 1 | 25 | 3.02 |
| Carlos Briseno-Vidrios | 2 | 5 | 3.31 |
| Junning Jiang | 3 | 4 | 2.12 |
| Chul-Hyun Park | 4 | 150 | 12.36 |
| Qiyuan Liu | 5 | 9 | 3.05 |
| Eric Soenen | 6 | 29 | 7.15 |
| Martin Kinyua | 7 | 16 | 4.11 |
| Jose Silva-Martinez | 8 | 630 | 86.56 |