A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator | 3 | 0.38 | 2020 |
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration | 0 | 0.34 | 2019 |
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. | 2 | 0.45 | 2018 |
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. | 1 | 0.40 | 2018 |
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. | 0 | 0.34 | 2017 |
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. | 3 | 0.48 | 2017 |
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications | 0 | 0.34 | 2017 |
A 13bit 200ms/S Pipeline Adc With Current-Mode Mdacs | 0 | 0.34 | 2017 |