Paper Info
Title
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits
Abstract
To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA’s process scalability by comparing the measured results of the DA-based MDAC prototyped in 65- and 28-nm CMOS. We observe <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times - 3\times $ </tex-math></inline-formula> improvement in speed, power, and area mainly resulting from the DA’s process scalability.
Year
DOI
Venue
2019
10.1109/TVLSI.2019.2924686
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
Gain,Capacitors,Calibration,Transistors,Thermal noise,Gain measurement,Wireless communication
Electrical efficiency,Computer science,Noise (electronics),Circuit design,Electronic engineering,Switched capacitor,CMOS,Transistor,Operational amplifier,Amplifier
Journal
Volume
Issue
ISSN
27
11
1063-8210
Citations 
PageRank 
References 
1
0.37
0
Authors
10
Name
Order
Citations
PageRank
Kentaro Yoshioka1549.04
Tomohiko Sugimoto2122.03
Naoya Waki321.09
SinNyoung Kim422.35
Daisuke Kurose5175.11
Hirotomo Ishii672.03
Masanori Furuta7223.56
Akihide Sai8208.25
Hiroki Ishikuro928552.15
Tetsuro Itakura1018733.44