Name
Title | ||
|---|---|---|
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization |
Abstract | ||
|---|---|---|
This paper proposes a hybrid time-voltage phase digitization technique in an all-digital phase-locked loop (ADPLL). To cover the required dynamic range of one oscillator period to measure the phase difference between clock edges of reference and feedback from a high-frequency oscillator, a digital-to-time converter (DTC) is used to reduce the required range of a time-to-digital converter (TDC). Further, a time error is first converted to voltage through a time-to-voltage converter (TVC) and further quantized to digital bits by a SAR-ADC. This results in a high-resolution phase detection which can help reducing the in-band phase noise while consuming low power. The system has been modeled and verified based on an event-driven approach in 28 nm CMOS. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/APCCAS47518.2019.8953166 | 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) |
Keywords | Field | DocType |
ADPLL,time-to-digital converter (TDC),SAR-ADC,phase noise,mm-wave,event-driven | Phase-locked loop,Oscillation,Dynamic range,Computer science,Voltage,Phase noise,Electronic engineering,CMOS,Successive approximation ADC,Phase detector | Conference |
ISBN | Citations | PageRank |
978-1-7281-2941-9 | 0 | 0.34 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vivek Govindaraj | 1 | 1 | 1.72 |
| Jianglin Du | 2 | 5 | 2.57 |
| Yizhe Hu | 3 | 9 | 3.93 |
| Teerachot Siriburanon | 4 | 149 | 21.47 |
| Robert Bogdan Staszewski | 5 | 536 | 93.76 |