Author Info
Name
Affiliation
Papers
YIZHE HU
Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China
11
Collaborators
Citations 
PageRank 
8
9
3.93
Referers 
Referees 
References 
32
52
16
Title
Citations
PageRank
Year
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL10.362021
A 24–31 GHz Reference Oversampling ADPLL Achieving FoM<inf>jitter−N</inf> of -269.3 dB00.342021
Oscillator Flicker Phase Noise: A Tutorial40.402021
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.00.342020
A 0.3V, 35% Tuning-Range, 60kHz 1/f<sup>3</sup>-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoM<inf>T</inf> of -199dB in 28-nm CMOS00.342019
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization00.342019
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications00.342019
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators.40.472019
A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path.00.342018
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner.00.342017
A Modeling Approach For Mixed-Mode Fmcw Synthesizer Allowing Frequency Error Analysis00.342015