Name
Abstract | ||
|---|---|---|
This paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent model of the PLL and expressions for random-noise and limit-cycle jitter are first derived for the case of a 2-bit time-to-digital converter with a mid-rise characteristic, and the optimal TDC resolution is determined. The analysis, which account for TDC mismatches, shows that, compared to the 1-bit one, the 2-bit time-to-digital converter can substantially reduce the quantization noise in the case of dominant random-walk noise at the TDC input. Moving to the
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N_{b}$ </tex-math></inline-formula>
-bit midrise TDC case, the quantization noise can be further reduced at the cost of higher complexity and finer time resolution. The choice of
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N_{b}=2$ </tex-math></inline-formula>
seems to be the best compromise between jitter reduction and complexity increase. Time-domain simulations assess the theoretical framework and demonstrate the validity of the assumptions made throughout the paper. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCSI.2019.2959252 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Digital phase locked loop,time-to-digital converter,jitter,bang-bang,phase detector | Journal | 67 |
Issue | ISSN | Citations |
3 | 1549-8328 | 3 |
PageRank | References | Authors |
0.38 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luca Avallone | 1 | 9 | 1.51 |
| M. P. Kennedy | 2 | 490 | 87.57 |
| Saleh Karman | 3 | 8 | 2.18 |
| Carlo Samori | 4 | 349 | 39.76 |
| Salvatore Levantino | 5 | 351 | 43.23 |