Title | ||
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17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. |
Abstract | ||
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Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1], [2] due to their ability to achieve ultra-low jitter (\u003c100fs). However, as indicated in Fig. 17.6.1 (top-left), sub-sampling PLLs (SS-PLL) typically suffer from high-power consumption, especially in mmW VCO buffers, which isolate the VCO from its sampler for reducing reference spurs, and in the high-speed dividers [2]–[4]. Also, the analog loop filter usually occupies large area. On the other hand, the IL technique for mmW frequency generation requires power-hungry high-frequency injection (~GHz) to fully suppress the oscillator phase noise [1], [4] and cannot ensure robustness over PVT (process, voltage, temperature) [4], which requires an additional frequency-tracking loop (FTL), see Fig. 17.6.1 (top-right). Furthermore, there exists a significant danger of a timing-race problem between the injection reference and FTL, since the frequency error may be corrected by IL before the FTL senses it. In [1], the FTL based on a phase averaging technique can solve the timing-race problem but requires a QVCO and an analog loop filter with relatively large area. |
Year | DOI | Venue |
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2020 | 10.1109/ISSCC19947.2020.9063024 | ISSCC |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 8 |
Name | Order | Citations | PageRank |
---|---|---|---|
Yizhe Hu | 1 | 9 | 3.93 |
Xi Chen | 2 | 2 | 1.37 |
Teerachot Siriburanon | 3 | 149 | 21.47 |
Jianglin Du | 4 | 5 | 2.57 |
Zhong Gao | 5 | 12 | 4.68 |
Vivek Govindaraj | 6 | 1 | 1.72 |
Anding Zhu | 7 | 18 | 10.46 |
Robert Bogdan Staszewski | 8 | 536 | 93.76 |