Paper Info
Title
A 66fs(Rms) Jitter 12.8-To-15.2ghz Fractional-N Bang-Bang Pll With Digital Frequency-Error Recovery For Fast Locking
Abstract
The substantial increase in mobile data-rates, enabled by the 5G standard, calls for significantly lower integrated jitter of the local oscillator with respect to previous generations, with requirements below 90fs rms for millimeter-wave frequency bands [1]. To satisfy such stringent requirements, while at the same time guaranteeing fast lock, analog PLLs have been preferred over digital implementations in recent literature [1], [2]. Digital bang-bang PLLs, on the other hand, consume less power and occupy smaller footprint due to the absence of analog loop filters. Digital bang-bang PLLs, however, generally suffer from poor locking performance, which is due to the bang-bang phase detector (BBPD) overloading in presence of large frequency errors, and from increased jitter due to quantization. To improve locking, [3] relies on additional frequency-locking loops (FLLs) to bypass the BBPD when overloaded, at the cost of additional design complexity and power. To improve on quantization noise, [4] proposes a digital PLL based on an enhanced-resolution time-to-digital converter (TDC). However, locking performances were not addressed, and its operation was limited to the integer-N mode. Achieving low-jitter in a fractional-N PLL poses an extra challenge, because of the random jitter introduced by the digital-to-time converter (DTC) and the spectrum folding of the DTC quantization noise arising from its non-linearity and memory effects [1].
Year
DOI
Venue
2020
10.1109/ISSCC19947.2020.9063094
2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC)
DocType
ISSN
Citations 
Conference
0193-6530
0
PageRank 
References 
Authors
0.34
0
8
Name
Order
Citations
PageRank
Alessio Santiccioli1173.01
Mario Mercandelli2154.32
Luca Bertulessi3154.73
Angelo Parisi411.70
Dmytro Cherniak5265.24
Andrea L. Lacaita632042.41
Carlo Samori734939.76
Salvatore Levantino835143.23