Paper Info
Title
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier
Abstract
Needs for I/O bandwidth have rapidly increased with the explosive growth of internet traffic and data technologies. To accommodate the required high bandwidth, a DSP-based PAM-4 transceiver became the most robust solution with increased usage of channel capacity [1]–[4]. However, to be integrated with many transceivers in a chip, low-power designs are becoming critical factors for DSP-based transceivers. This paper presents an MM-CDR-based ADC timing skew control, which greatly reduces ADC complexity and power, and a low-power DSP using an approximate multiplier. Besides this, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{g}_{\mathrm{m}}$</tex> boosting of the TX driver and low-power TX DAC help reduce total power consumption.
Year
DOI
Venue
2020
10.1109/ISSCC19947.2020.9062964
2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Keywords
DocType
ISSN
power consumption,low-power TX DAC,TX driver,gm boosting,ADC complexity,channel capacity,I/O bandwidth,low-power designs,DSP-based PAM-4 transceiver,data technologies,Internet traffic,approximate multiplier,low-power DSP,MM-CDR-based ADC timing skew control,FinFET,PAM-4 wireline transceiver,size 10.0 nm,bit rate 56 Gbit/s
Conference
0193-6530
ISBN
Citations 
PageRank 
978-1-7281-3206-8
0
0.34
References 
Authors
0
19
Name
Order
Citations
PageRank
Byoung-Joo Yoo101.01
Dong-Hyuk Lim2152.82
Hyonguk Pang300.34
Junehee Lee422.56
Seung-Yeob Baek541.51
Naxin Kim600.34
Dong-Ho Choi711.03
Young-Ho Choi801.01
Hyeyeon Yang900.34
Taehun Yoon10163.60
Sang-Hyeok Chu11112.01
Kangjik Kim1200.34
Woochul Jung1300.34
Bong-Kyu Kim1400.34
Jaechol Lee1500.34
Gunil Kang1601.01
Sanghune Park1713.06
Michael Choi18499.96
jongshin shin1974.33