Paper Info
Title
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator
Abstract
A digitally assisted high-current low-dropout (LDO) regulator is proposed in this article. The LDO architecture combines two main types of regulators: digital LDOs and analog LDOs. The proposed architecture uses the digital loop for tracking large output current variations and the analog loop for steady-state operation. The dual loops have a loop controller for coherent operation. Hence, the proposed LDO inherits some advantages from both sides. It achieves high power supply rejection (PSR) from the analog part without ripples at the output. Compared with the analog loop, the digital loop has a faster settling time while consuming minimum static power. In this design, the maximum load is 245 mA. The PSR is −42 dB at 1 MHz for heavy loading conditions. The quiescent current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}{Q}$ </tex-math></inline-formula> ) is 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> . When the 300-/100-ns (rising/falling) current step is applied at the load, the voltage peak is 71/37 mV, respectively. The proposed LDO achieves a competitive 7.4-ps figure of merit (FOM). The active area is approximately 0.056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a TSMC40-nm process.
Year
DOI
Venue
2020
10.1109/JSSC.2020.2987718
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Transistors,Logic gates,Computer architecture,Clocks,Regulators,Tracking loops,Steady-state
Journal
55
Issue
ISSN
Citations 
8
0018-9200
3
PageRank 
References 
Authors
0.38
0
6
Name
Order
Citations
PageRank
Dadian Zhou130.38
Junning Jiang242.12
Qiyuan Liu393.05
Eric Soenen4297.15
Martin Kinyua5164.11
Jose Silva-Martinez663086.56