Title
Approximate Multipliers With Dynamic Truncation For Energy Reduction Via Graceful Quality Degradation
Abstract
In approximate operators, dynamic truncation allows trading off energy and quality of computation at runtime. Although it exploits the specificity of the data being processed, its significant energy overhead over simple static truncation fundamentally limits its energy benefits. This brief describes a simple and efficient design methodology that reduces the energy consumption of dynamically truncated multipliers, based on a smart mapping of the partial products. A configurable hardware correction strategy is also proposed to enable graceful quality degradation, as well as more aggressive energy reduction at a given quality. When applied to Wallace multipliers, the proposed approach achieves quality, in terms of Mean Error Distance, up to 11x higher than the conventional dynamic truncation, at the same energy. In the case study of Discrete Cosine Transform compression, the proposed approximate multiplier reaches image qualities by 15-35% better, compared to prior art.
Year
DOI
Venue
2020
10.1109/TCSII.2020.2999131
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Keywords
DocType
Volume
Logic gates, Image coding, Runtime, Hardware, Energy consumption, Design methodology, Degradation, Energy-quality scaling, approximate computing, multiplier, low-power design, VLSI
Journal
67
Issue
ISSN
Citations 
12
1549-7747
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Fabio Frustaci112917.55
Stefania Perri226433.11
Pasquale Corsonello327838.06
Massimo Alioto470688.98