Paper Info
Title
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions
Abstract
This article presents a high-performance annealing processor named STochAsTIc Cellular automata Annealer (STATICA) for solving combinatorial optimization problems represented by fully connected graphs. Supporting fully connected graphs is strongly required for dealing with realistic optimization problems. Unlike previous annealing processors that follow Glauber dynamics, our proposed annealer can update multiple states of fully connected spins simultaneously by introducing different dynamics called stochastic cellular automata annealing. It allows us to utilize the pipeline-level and memory-bank-level parallelization in addition to the PE-level parallelization originally adopted in the previous annealers. The STATICA prototype chip, which supports 512-spin fully connected graph, has been fabricated with the 65-nm CMOS technology and realized as a 3 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times \,\,{4}$ </tex-math></inline-formula> mm chip. Using the fabricated 512-spin chip and numerical projections for a 2048-spin chip, we have conducted experiments to reveal the annealing performance of STATICA and examined how to control its annealing process efficiently.
Year
DOI
Venue
2021
10.1109/JSSC.2020.3027702
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Annealing processor,CMOS-based annealing chip,combinatorial optimization,fully connected Ising model,processor architecture
Journal
56
Issue
ISSN
Citations 
1
0018-9200
2
PageRank 
References 
Authors
0.52
2
10
Name
Order
Citations
PageRank
Kasho Yamamoto131.97
Kazushi Kawamura232.58
Kota Ando3246.81
Normann Mertig431.63
Takashi Takemoto59919.11
Masanao Yamaoka612823.39
Hiroshi Teramoto732.64
Akira Sakai831.63
Shinya Takamaeda-Yamazaki96516.83
Masato Motomura109127.81