Paper Info
Title
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-<italic>N</italic> Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
Abstract
This article presents a fractional-N frequency synthesizer architecture that is able to overcome the limitations of conventional bang-bang phase-locked loops. A digital frequencyerror recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jitter and low-spur fractional-N operation. The phase-locked loop (PLL), implemented in a standard 28-nm CMOS process, occupies a core area of 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It covers a 1-GHz hop to within 70 ppm of the steady-state frequency value in 18.55 μs. The prototype achieves an rms-jitter (integrated from 1 kHz to 100 MHz) of 66.20 and 58.96 fs, in the fractional-N and integer-N modes, respectively. The worst-case in-band fractional spur is at -61 dBc. The total power consumption is 19.8 mW, which leads to a jitter-power figure-of-merit of -250.6 dB for the fractional-N channels.
Year
DOI
Venue
2020
10.1109/JSSC.2020.3019344
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Bang–bang phase detector (BBPD),digital-to-time converter (DTC),digital phase-locked loop (DPLL),fast-locking,fifth-generation (5G) fractional-N,frequency synthesizer,low-jitter,phase-locked loop (PLL)
Journal
55
Issue
ISSN
Citations 
12
0018-9200
1
PageRank 
References 
Authors
0.35
20
8
Name
Order
Citations
PageRank
Alessio Santiccioli1173.01
Mario Mercandelli2154.32
Luca Bertulessi3154.73
Angelo Parisi411.70
Dmytro Cherniak5265.24
Andrea L. Lacaita632042.41
Carlo Samori734939.76
Salvatore Levantino835143.23