Name
Abstract | ||
|---|---|---|
This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-for... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/JSSC.2021.3101046 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Phase locked loops,Oscillators,Jitter,Clocks,Calibration,Perturbation methods,Crystals | Journal | 56 |
Issue | ISSN | Citations |
11 | 0018-9200 | 1 |
PageRank | References | Authors |
0.36 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jianglin Du | 1 | 5 | 2.57 |
| Teerachot Siriburanon | 2 | 149 | 21.47 |
| Yizhe Hu | 3 | 9 | 3.93 |
| Vivek Govindaraj | 4 | 1 | 1.72 |
| Robert Bogdan Staszewski | 5 | 536 | 93.76 |