Title
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW
Abstract
This paper presents a systematic design framework for ADC optimization. Our emphasis is on a robust design that is highly repeatable, which is driven by a deep understanding of the behavior of circuit building blocks. A 10 b 500 MS/s single-channel SAR ADC designed in this framework displays uniform performance for inputs up to 2 GHz at state-of-the-art FoM, which demonstrates the power of design ...
Year
DOI
Venue
2021
10.1109/ESSCIRC53450.2021.9567842
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Keywords
DocType
ISSN
Systematics,Conferences,Europe,Tutorials,Solid state circuit design,Tools,Frequency conversion
Conference
1930-8833
ISBN
Citations 
PageRank 
978-1-6654-3751-6
1
0.36
References 
Authors
0
3
Name
Order
Citations
PageRank
Tetsuya Iizuka19233.22
Hao Xu210.36
Asad A. Abidi31401532.51