Name
Abstract | ||
|---|---|---|
Cache memories are an indispensable component of many processor-based systems and contribute significantly to the overall area, power consumption, and delay. This leads to an important role played by modeling tools for estimating the area, power consumption, and access time of cache memories. However, existing modeling tools such as CACTI and its various extensions have been primarily designed usi... |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/TVLSI.2021.3123112 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
Transistors,FinFETs,Capacitance,Logic gates,Power demand,Integrated circuit modeling,Data models | Journal | 30 |
Issue | ISSN | Citations |
3 | 1063-8210 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Divya Praneetha Ravipati | 1 | 0 | 0.34 |
| Rajesh Kedia | 2 | 0 | 0.34 |
| Victor M. Van Santen | 3 | 0 | 0.34 |
| J. Henkel | 4 | 4471 | 366.50 |
| Preeti Ranjan Panda | 5 | 786 | 89.40 |
| Hussam Amrouch | 6 | 251 | 50.22 |