Name
Title | ||
|---|---|---|
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise |
Abstract | ||
|---|---|---|
This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115
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, overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/TCSI.2022.3146788 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Digital phase-locked loop (DPLL),digital to time converter (DTC),frequency synthesis,locking aid,locking time,phase noise | Journal | 69 |
Issue | ISSN | Citations |
5 | 1549-8328 | 0 |
PageRank | References | Authors |
0.34 | 18 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luca Bertulessi | 1 | 0 | 0.34 |
| Dmytro Cherniak | 2 | 0 | 0.34 |
| Mario Mercandelli | 3 | 15 | 4.32 |
| Carlo Samori | 4 | 349 | 39.76 |
| Andrea L. Lacaita | 5 | 320 | 42.41 |
| Salvatore Levantino | 6 | 351 | 43.23 |