Paper Info
Title
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory
Abstract
We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based algorithm with 6.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> improvement in synchronization latency. Measured on a diverse set of compute kernels, Versa’s design features culminate in median energy-efficiency improvements of 37.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> and 11.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> over mobile CPU and GPU baselines, respectively.
Year
DOI
Venue
2022
10.1109/JSSC.2022.3140241
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Accelerators,data movement,data reuse,energy efficiency,interconnect,multicore architecture,on-chip memory,programmability,reconfiguration,systolic arrays
Journal
57
Issue
ISSN
Citations 
4
0018-9200
0
PageRank 
References 
Authors
0.34
27
13
Name
Order
Citations
PageRank
Sung Kim100.34
Morteza Fayazi200.34
Alhad Daftardar300.34
Kuan-Yu Chen411.02
Jielun Tan500.34
Subhankar Pal600.34
Tutu Ajayi7203.28
Yan Xiong801.01
Trevor Mudge96139659.74
Chaitali Chakrabarti101978184.17
David Blaauw118916823.47
Ronald G. Dreslinski12125881.02
Hun-Seok Kim1301.01