Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory | 0 | 0.34 | 2022 |
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm | 1 | 0.35 | 2021 |
Bridging Academic Open-Source EDA to Real-World Usability. | 1 | 0.35 | 2020 |
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. | 0 | 0.34 | 2020 |
An Open-source Framework for Autonomous SoC Design with Analog Block Generation | 0 | 0.34 | 2020 |
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project | 9 | 0.63 | 2019 |
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS | 0 | 0.34 | 2019 |
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. | 9 | 0.59 | 2018 |