Name
Title | ||
|---|---|---|
Universal Pre-Calculating Structure: Reducing Complexity of Ising Chips with Arbitrary Connectivity |
Abstract | ||
|---|---|---|
Combinatorial optimization problems widely exist in real-world application fields, such as intelligence computation. Solving combinatorial optimization problems is a great challenge for Von Neumann-architecture computers. Alternatively, the Ising chip is a promising solution for combinatorial optimization problems. However, the complexity of the next-spin calculation module greatly increase the hardware cost of the Ising chip. In this paper, we propose universal pre-calculating structures to simplify the next-spin calculating module for the Ising chip with arbitrary connectivity ranging from local to full connectivity. We establish a cost model to provide 1) fast and precise evaluation of hardware cost, and 2) guidelines to select the most suitable structure towards a certain design target. The hardware cost evaluation on FPGA agrees well with our cost model, and shows that our pre-calculating structure can reduce the total cost of Ising chips by 20%. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/DSC53577.2021.00040 | 2021 IEEE Sixth International Conference on Data Science in Cyberspace (DSC) |
Keywords | DocType | ISBN |
Ising Model,CMOS Circuit,Combinatorial Optimization Problem,Computer Architecture | Conference | 978-1-6654-1816-4 |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jian Zhang | 1 | 12 | 26.99 |
| Linghui Lv | 2 | 0 | 0.34 |
| Zhi Wang | 3 | 1 | 0.70 |
| Ying Zhang | 4 | 163 | 25.25 |
| Yang Yang | 5 | 612 | 174.82 |
| Jinjiu Li | 6 | 0 | 0.34 |
| Yaohua Wang | 7 | 44 | 14.23 |