Seung-Wook Kwack - Citegraph

Author Info

Name	Affiliation	Papers
SEUNG-WOOK KWACK	Hanyang Univ, Dept Elect & Comp Engn, Semicond Lab, Seoul 133791, South Korea	5
Collaborators	Citations	PageRank
44	18	2.78
Referers	Referees	References
113	151	14

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100151

Publications (5 rows)

Collaborators (44 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector	3	0.45	2014
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.	1	0.40	2009
A High Speed Graphics Dram With Low Power And Low Noise Data Bus Inversion In 54nm Cmos	0	0.34	2009
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.	9	0.94	2008
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.	5	0.65	2008

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