A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

Paper Info

Title
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

Year	DOI	Venue
2008	10.1109/ISSCC.2008.4523167	ISSCC
Keywords	Field	DocType
cmos technology,duty cycle,cmos integrated circuits,digital controller	Dual loop,Dram,Duty cycle,Computer science,Clock domain crossing,CMOS,Input/output,Electronic engineering,Synchronous circuit,Detector	Conference
Citations	PageRank	References
9	0.94	2
Authors
22

Authors (22 rows)

Cited by (9 rows)

References (2 rows)

Name	Order	Citations	PageRank
Won-Joo Yun	1	53	8.30
Hyun-Woo Lee	2	162	43.02
Dongsuk Shin	3	66	10.08
Shin-Deok Kang	4	25	3.90
Ji-Yeon Yang	5	10	1.34
Hyeng-Ouk Lee	6	10	1.34
Dong-Uk Lee	7	23	2.68
Su-jeong Sim	8	11	1.71
Young-Ju Kim	9	268	29.56
Won Jun Choi	10	14	3.58
Keun-Soo Song	11	20	3.14
Sang-Hoon Shin	12	15	1.99
Hyang-Hwa Choi	13	10	1.34
Hyung-Wook Moon	14	10	1.34
Seung-Wook Kwack	15	18	2.78
Jungwoo Lee	16	1467	156.34
Young-Kyoung Choi	17	17	2.73
Nak-Kyu Park	18	17	2.73
Kwan-Weon Kim	19	44	6.51
Young-Jung Choi	20	63	9.75
Jin-Hong Ahn	21	15	2.85
Ye Seok Yang	22	14	1.59