Maoxiang Yi - Citegraph

Author Info

Name	Affiliation	Papers
MAOXIANG YI	Hefei University of Technology, China	25
Collaborators	Citations	PageRank
67	28	9.14
Referers	Referees	References
73	276	117

Search Limit

100276

Publications (25 rows)

Collaborators (67 rows)

Referers (73 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A reconfigurable PUF structure with dual working modes based on entropy separation model	0	0.34	2022
Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator	0	0.34	2022
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	0	0.34	2022
A reconfigurable test method based on LFSR for 3D stacking integrated circuits	0	0.34	2022
High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure	2	0.36	2021
Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator	1	0.36	2021
A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.	1	0.35	2019
Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory	0	0.34	2019
A Pulse Shrinking-based Test Solution for Pre-bond Through Silicon Via in 3D ICs	1	0.36	2019
An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs	0	0.34	2018
A High Reliability FPGA Chip Identification Generator Based on PDLs	0	0.34	2018
A Low-Cost High-Efficiency True Random Number Generator on FPGAs	0	0.34	2018
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique	0	0.34	2018
Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS	0	0.34	2018
A Single Event Transient Detector In Sram-Based Fpgas	1	0.40	2017
A Highly Reliable Butterfly Puf In Sram-Based Fpgas	0	0.34	2017
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.	6	0.48	2017
An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator.	0	0.34	2017
Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect	0	0.34	2016
NBTI-induced circuit aging optimization by protectability-aware gate replacement technique	1	0.36	2015
A Self-Recoverable, Frequency-Aware And Cost-Effective Robust Latch Design For Nanoscale Cmos Technology	9	0.60	2015
Decreasing SoC Test Power Dissipation and Test Data Volume Based on Pattern Recombination	0	0.34	2011
A novel x-ploiting strategy for improving performance of test data compression	2	0.36	2010
Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing	0	0.34	2009
A BIST Scheme Based on Selecting State Generation of Folding Counters	4	0.44	2005