Name
Abstract | ||
|---|---|---|
Upcoming processor generations increasingly provideinstructions for sub-word parallelism. Thus, a parallel executionof 2, 4 or 8 instructions (add, sub) or of complexinstructions (sum of differences) with an input of 2, 4 or 8operand pairs becomes possible. The exploitation of sub-wordparallelism is still weakly supported by current compilers.To remedy this we have adapted methods from thedesign of parallel regular processor arrays. The causal-ityconstraints which influence the design flow of processorarrays can be relaxed for processors with sub-word parallelism.An algorithm calculating the Mahalanobis distanceis used to illustrate the influence.Based on this extended approach, we have obtained significantspeed-ups of our test-vehicle, of up to a factor 3 onan Intel P4. In the conventional approach, assembly-levelcoding would have been required to achieve this. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/DSD.2003.1231904 | DSD |
Keywords | Field | DocType |
sub-word parallelism,design flow,extended approach,current compiler,parallel regular processor array,causality constraints,parallel executionof,mahalanobis distanceis,upcoming processor generation,processor architectures,conventional approach,onan intel p4,computer architecture,parallel programming,processor architecture,mahalanobis distance,causality | Instruction-level parallelism,Cellular architecture,Implicit parallelism,Computer science,Task parallelism,Operand,Parallel computing,Compiler,Design flow,Data parallelism | Conference |
ISBN | Citations | PageRank |
0-7695-2003-0 | 2 | 0.39 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rainer Schaffer | 1 | 29 | 5.30 |
| Renate Merker | 2 | 159 | 20.59 |
| Francky Catthoor | 3 | 3932 | 423.30 |