Paper Info
Title
Systematic Design of Programs with Sub-Word Parallelism
Abstract
Upcoming processor generations increasingly provide instructions for sub-word parallelism. Thus, a parallel execution of 2, 4 or 8 instructions (add, sub) or of complex instructions (sum of differences) with an input of 2, 4 or 8 operand pairs becomes possible. The exploitation of sub-word parallelism is still weakly supported by current compilers. To close this gap we present an approach to generate programs for processors with sub-word parallelism. To this end we adapt methods from the design of parallel processor arrays. An algorithm representinga short term analysis filtering is used to illustrate the approach.
Year
DOI
Venue
2002
10.1109/PCEE.2002.1115305
PARELEC
Keywords
Field
DocType
sub-word parallelism,complex instruction,parallel execution,current compiler,upcoming processor generation,algorithm representinga short term,parallel processor array,operand pair,systematic design,generic programming,algorithm design and analysis,digital signal processing,process design,parallel programming,parallel processing,design methodology,compilers,instruction sets,difference equations
Instruction-level parallelism,Implicit parallelism,Computer science,Instruction set,Task parallelism,Operand,Parallel computing,Data parallelism,Scalable parallelism,Memory-level parallelism
Conference
ISBN
Citations 
PageRank 
0-7695-1730-7
5
0.50
References 
Authors
5
3
Name
Order
Citations
PageRank
Rainer Schaffer1295.30
Renate Merker215920.59
Francky Catthoor33932423.30