Name
Title | ||
|---|---|---|
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. |
Abstract | ||
|---|---|---|
This brief presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700-840 MHz at VDD = 1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 μW/MHz per node is 7 times lower than tha... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCSII.2019.2932029 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Phase frequency detector,Clocks,Oscillators,Synchronization,Phase locked loops,Detectors,Frequency synchronization | Phase-locked loop,Clock generator,Oscillation,Synchronization,Electronic engineering,CMOS,Electrical engineering,Detector,Mathematics,Scalability,Phase frequency detector | Journal |
Volume | Issue | ISSN |
66 | 10 | 1549-7747 |
Citations | PageRank | References |
1 | 0.48 | 0 |
Authors | ||
10 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dimitri Galayko | 1 | 81 | 26.41 |
| Chuan Shan | 2 | 12 | 3.55 |
| Eldar Zianbetov | 3 | 33 | 7.71 |
| Mohammad Javidan | 4 | 9 | 2.59 |
| Anton Korniienko | 5 | 9 | 4.52 |
| François Anceau | 6 | 8 | 2.69 |
| Olivier Billoint | 7 | 33 | 8.59 |
| Éric Colinet | 8 | 1 | 0.48 |
| Elena Blokhina | 9 | 27 | 19.12 |
| Jérôme Juillard | 10 | 1 | 0.48 |