Name
Title | ||
|---|---|---|
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets |
Abstract | ||
|---|---|---|
We report on muon-induced single event upsets (SEU) in SRAMs built on 32nm planar and 22nm and 14nm 3D Tri-Gate technologies. Experimental cross sections were measured using the M20C positive muon beamline at TRIUMF. Physics-based simulations were conducted to estimate sea-level SEU rates for both, positive and negative muons. Our results indicate that a) the muon induced upset rate is negligible compared to neutron induced upset rate, and b) the introduction of 3D Tri-Gate transistors reduced the susceptibility to muons by approximately two orders of magnitude relative to 32nm planar cross sections. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/IRPS.2015.7112676 | Reliability Physics Symposium |
Keywords | Field | DocType |
sram chips,muons,radiation hardening (electronics),three-dimensional integrated circuits,3d trigate transistor technology,m20c positive muon beamline,seu,sram,triumf,muon-induced single event upset,negative muon,physics-based simulation,planar technology,sea-level seu rate estimation,size 14 nm,size 22 nm,size 32 nm,tri-gate cmos,accelerated testing,muon,planar,single event upset,mesons,neutrons,acceleration,atmospheric modeling | Beamline,Neutron,Meson,Muon,Electronic engineering,Planar,Upset,Nuclear physics,Transistor,Order of magnitude,Physics | Conference |
ISSN | Citations | PageRank |
1541-7026 | 0 | 0.34 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Norbert Seifert | 1 | 285 | 18.97 |
| Shah M. Jahinuzzaman | 2 | 49 | 6.08 |
| Jyothi Velamala | 3 | 53 | 4.83 |
| Nikunj Patel | 4 | 0 | 0.34 |