Paper Info
Title
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters
Abstract
In the context of high-performance computing and big-data applications, the quest for performance requires modular, scalable, energy-efficient, low-cost manycore systems. Partitioning the system into multiple chiplets 3D-stacked onto large-scale interposers - organic substrate [1], 2.5D passive interposer [2] or silicon bridge [3] -leads to large modular architectures and cost reductions in advanced technologies by the Known Good Die (KGD) strategy and yield management. However, these approaches lack flexible efficient long-distance communications, smooth integration of heterogeneous chiplets, and easy integration of less-scalable analog functions, such as power management [4] and system IOs. To tackle these issues, this paper presents an active interposer integrating: i) a Switched Capacitor Voltage Regulator (SCVR) for on-chip power management; ii) flexible system interconnect topologies between all chiplets for scalable cache coherency support; iii) energy-efficient 3D-plugs for dense inter-layer communication; iv) a memory-IO controller and PHY for socket communication. The chip (Fig. 2.3.7) integrates 96 cores in 6 chiplets in 28nm FDSOI CMOS, 30-stacked in a face-to-face configuration using 20μm-pitch micro-bumps (μ-bumps) onto a 200 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active interposer with 40μm-pitch Through Silicon Via (TSV) middle in a 65nm technology node. Even though complex functions are integrated, active-interposer yield is high thanks to the mature 65nm node and a reduced complexity (0.08transistors/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), with 30% of interposer area devoted to a SCVR variability-tolerant capacitors scheme.
Year
DOI
Venue
2020
10.1109/ISSCC19947.2020.9062927
2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Keywords
DocType
ISSN
220GOPS 96-core processor,DC-DC converters,high-performance computing,big-data applications,large-scale interposers,organic substrate,2.5D passive interposer,silicon bridge,modular architectures,cost reductions,yield management,long-distance communications,heterogeneous chiplets,less-scalable analog functions,power management,active interposer integrating,Switched Capacitor Voltage Regulator,on-chip power management,scalable cache coherency support,memory-IO controller,socket communication,microbumps,active-interposer yield,interchiplet interconnects,dense interlayer communication,Known Good Die strategy,KGD strategy,through silicon via,TSV,energy-efficient 3D-plugs,SCVR variability-tolerant capacitors scheme,FDSOI CMOS,size 28.0 nm,size 65.0 nm,size 20 mum,size 40 mum
Conference
0193-6530
ISBN
Citations 
PageRank 
978-1-7281-3206-8
0
0.34
References 
Authors
2
28
Name
Order
Citations
PageRank
Pascal Vivet160653.09
Eric Guthmuller2193.80
Yvain Thonnart334932.39
Gael Pillonnet42412.54
guillaume moritz561.90
Ivan Miro-Panadès630.79
César Fuguet Tortolero752.89
Jean Durupt8556.43
Christian Bernard9465.36
Didier Varreau10885.66
Julian J. H. Pontes11495.82
Sebastien Thuries12277.32
David Coriat1341.50
Michel Harrand1430.79
Denis Dutoit151599.35
Didier Lattard1614418.68
L. Arnaud17152.97
Jean Charbonnier1800.34
P. Coudrain19205.00
Arnaud Garnier2071.69
Frederic Berger2130.79
Alain Gueugnot2230.79
Alain Greiner2331.13
Quentin Meunier24105.31
Alexis Farcy25165.88
Alexandre Arriordaz2651.26
Séverine Cheramy27224.74
Fabien Clermidy2879761.56