Name
Abstract | ||
|---|---|---|
This paper shows that double gate devices, like independent-gate (IG) FinFETs, have introduced new challenges in the transistor network generation step during the logic synthesis. The main point is that reducing the number of literals in a given Boolean expression is not enough to guarantee a minimum IG FinFET network implementation. This way, traditional factorization methods or graph-based optimizations may not be useful to generate networks for double gate devices. In this sense, this paper presents a graph-based method able to find promising arrangements to explore the separated gates of each IG FinFET. The experiments demonstrate that the proposed method can reduce the number of IG FinFETs compared to the traditional methods of transistor network generation. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2660540.2661009 | SBCCI |
Keywords | Field | DocType |
algorithms,design,eda,factorization,logic gate,design aids,transistor network,logic synthesis,theory,graph theory,finfet | Logic synthesis,Logic gate,Pass transistor logic,Computer science,AND-OR-Invert,Electronic engineering,NOR logic,Logic family,Transistor,Boolean expression | Conference |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinicius Neves Possani | 1 | 11 | 3.04 |
| André Inácio Reis | 2 | 134 | 21.33 |
| Renato P. Ribas | 3 | 204 | 33.52 |
| Felipe de Souza Marques | 4 | 34 | 9.47 |
| Leomar Soares da Rosa Jr. | 5 | 8 | 5.35 |