Name
Abstract | ||
|---|---|---|
This paper presents an improvement in our previous methodology to generate efficient transistor networks. The proposed method applies graph-based optimizations and is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The main feature of our methodology is the possibility to avoid greedy choices during the beginning of the optimization process. This property is associated to an edges compression technique that also contributes to minimize the bad effect of the greedy choices. Performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/SBCCI.2013.6644854 | Integrated Circuits and Systems Design |
Keywords | Field | DocType |
graph theory,logic design,logic gates,optimisation,edges compression technique,graph-based optimizations,greedy choices,nonseries-parallel transistor arrangements,reduced transistor count,transistor networks,CMOS,EDA,Logic synthesis,VLSI design,digital design,logic gate,transistor network | Graph theory,Transistor count,Diode–transistor logic,Sequential logic,Multiple-emitter transistor,Pass transistor logic,Logic optimization,Computer science,Electronic engineering,Transistor | Conference |
Citations | PageRank | References |
2 | 0.41 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinicius Neves Possani | 1 | 11 | 3.04 |
| Vinicius Callegaro | 2 | 31 | 6.40 |
| André Inácio Reis | 3 | 134 | 21.33 |
| Renato P. Ribas | 4 | 204 | 33.52 |
| Felipe de Souza Marques | 5 | 34 | 9.47 |
| Leomar S. da Rosa Jr. | 6 | 25 | 4.75 |