William N. N. Hung

Author Info

Name	Affiliation	Papers
WILLIAM N. N. HUNG	Synopsys Incorporated(Synopsys Inc.,Synopsys, Inc.,Synopsys, Inc,Synopsys Inc),Mountain View,United States	65
Collaborators	Citations	PageRank
77	304	34.98
Referers	Referees	References
588	1046	724

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1001000

Publications (65 rows)

Collaborators (77 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Group Algebraic Approach to NPN Classification of Boolean Functions	2	0.37	2019
A New Pairwise NPN Boolean Matching Algorithm Based on Structural Difference Signature.	0	0.34	2019
Challenges in Large FPGA-based Logic Emulation Systems.	4	0.44	2018
Temporal Coverage Analysis for Dynamic Verification.	0	0.34	2018
An Efficient NPN Boolean Matching Algorithm Based on Structural Signature and Shannon Expansion.	3	0.40	2017
A Canonical-based NPN Boolean Matching Algorithm Utilizing Boolean Difference and Cofactor Signature.	1	0.35	2017
Computing Affine Equivalence Classes of Boolean Functions by Group Isomorphism.	4	0.41	2016
A Synthesis Method of Quantum Reversible Logic Circuit Based on Elementary Qutrit Quantum Logic Gates	1	0.36	2015
Pareto optimal mapping for tile-based network-on-chip under reliability constraints	0	0.34	2015
A multipartite entanglement measure based on coefficient matrices	2	0.42	2015
A Quantitative Characterization of Cross Coverage	1	0.36	2015
Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq	0	0.34	2015
A Case Study on Formal Analysis of an Automated Guided Vehicle System.	7	0.61	2014
Motion planning with Satisfiability Modulo Theories	3	0.40	2014
Combining Symmetry Reduction with Generalized Symbolic Trajectory Evaluation.	0	0.34	2014
Symbolic Analysis of Programmable Logic Controllers	3	0.39	2014
Performance-driven assignment and mapping for reliable networks-on-chips.	2	0.36	2014
Performance-driven assignment and mapping for reliable networks-on-chips.	2	0.36	2014
A Transformation-Based Approach to Implication of GSTE Assertion Graphs.	0	0.34	2013
Exponential-Condition-Based barrier certificate generation for safety verification of hybrid systems	16	0.92	2013
Reliable Node Clustering for Mobile Ad Hoc Networks.	3	0.43	2013
Complete Boolean Satisfiability Solving Algorithms Based on Local Search	1	0.35	2013
Complete Boolean Satisfiability Solving Algorithms Based on Local Search	1	0.35	2013
Bayesian-Network-Based Reliability Analysis of PLC Systems	7	0.53	2013
Optimizing communication in mobile ad hoc network clustering	6	0.49	2013
Verification and Implementation of the Protocol Standard in Train Control System	3	0.44	2013
System reliability calculation based on the run-time analysis of ladder program	1	0.37	2013
Maxterm Covering for Satisfiability	4	0.42	2012
New strategies for reliability analysis of Programmable Logic Controllers.	1	0.39	2012
Reliable noc mapping based on scatter search	1	0.34	2012
Uncertain Model and Algorithm for Hardware/Software Partitioning	12	0.64	2012
Reliability Analysis of PLC Systems by Bayesian Network	1	0.39	2012
Complete SAT solver based on set theory	0	0.34	2012
A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL	2	0.43	2011
Exploring structural symmetry automatically in symbolic trajectory evaluation	0	0.34	2011
Realization and synthesis of reversible functions	2	0.39	2011
Mathematical analysis of stage-based programmable logic controller	0	0.34	2011
Enhanced symbolic simulation of a round-robin arbiter	2	0.41	2011
A novel fault diagnosis mechanism for wireless sensor networks	15	0.70	2011
Domain-driven probabilistic analysis of programmable logic controllers	1	0.38	2011
Combining theorem proving and symbolic trajectory evaluation in THM&STE	0	0.34	2011
Compositional Abstraction Refinement for Timed Systems	2	0.39	2010
Synthesizing hybrid quantum circuits without ancilla qudits	0	0.34	2010
Integrating Evolutionary Computation with Abstraction Refinement for Model Checking	11	0.60	2010
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping	5	0.67	2010
Data mining based decomposition for assume-guarantee reasoning	3	0.37	2009
Minimal universal library for n×n reversible circuits	0	0.34	2008
Bi-Directional Synthesis of 4-Bit Reversible Circuits	16	0.92	2008
Defect-Tolerant CMOL Cell Assignment via Satisfiability	12	0.85	2007
Group theory based synthesis of binary reversible circuits	12	0.84	2006

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