Gian-Carlo Cardarilli

Author Info

Name	Affiliation	Papers
GIAN-CARLO CARDARILLI	Dept. of Electron. Eng., Univ. of Rome Tor Vergata, Rome, Italy\|c\|	32
Collaborators	Citations	PageRank
52	57	14.97
Referers	Referees	References
111	165	87

Search Limit

100165

Publications (32 rows)

Collaborators (52 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning.	0	0.34	2019
A Wireless Sensor Node for Acoustic Emission Non-destructive Testing.	0	0.34	2017
FPGA Implementation of a Low-Power QRS Extractor.	0	0.34	2017
Digital Architecture of Next Generation Spacecraft Tracker Based on Wideband ∆DOR.	0	0.34	2017
Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach	0	0.34	2016
A hardware framework for on-chip FPGA acceleration	1	0.36	2016
ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior	0	0.34	2016
A Wireless Sensor Node Based on Microbial Fuel Cell	0	0.34	2015
Characterization of RNS multiply-add units for power efficient DSP	1	0.35	2015
Twenty years of research on RNS for DSP: Lessons learned and future perspectives	0	0.34	2014
TDES cryptography algorithm acceleration using a reconfigurable functional unit	0	0.34	2014
Truncated multipliers through power-gating for degrading precision arithmetic	2	0.46	2013
A Reconfigurable Functional Unit for Modular Operations.	0	0.34	2013
High Performance Bit-Stream Decompressor for Partial Reconfigurable FPGAs.	0	0.34	2013
Compressive sensing spectrum analysis for space autonomous radio receivers	0	0.34	2013
Power efficient design of parallel/serial FIR filters in RNS	2	0.46	2012
Karatsuba implementation of FIR filters	0	0.34	2012
Imprecise arithmetic for low power image processing	10	0.69	2012
Fine-grain Reconfigurable Functional Unit for embedded processors	1	0.43	2011
Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit	4	0.72	2010
ADAPTO: full-adder based reconfigurable architecture for bit level operations	4	0.67	2008
Concurrent Error Detection in Reed–Solomon Encoders and Decoders	8	0.60	2007
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter	5	0.49	2005
A self checking Reed Solomon encoder: design and analysis	7	0.84	2005
FPGA implementation of a general purpose HMM processor based on token passing algorithm	1	0.36	2005
A fault tolerant hardware based file system manager for solid state mass memory	1	0.44	2003
Power-delay tradeoffs in residue number system	2	0.63	2003
A CAD environment for fuzzy systems HW/SW mapping	1	0.37	2000
Development of an evaluation model for the design of fault-tolerant solid state mass memory	4	0.81	2000
Failure tests on 64 Mb SDRAM in radiation environment	3	1.23	1999
A low-voltage reduced-power constant-gm rail-to-rail fully differential CMOS op-amp	0	0.34	1996
RNS Fourier transforms	0	0.34	1988