Name
Abstract | ||
|---|---|---|
In this paper, a high-performance data-path for accelerating DSP kernels is proposed. The data-path is based on a flexible, universal, and regular component that allows to optimally exploiting both inter- and intra-component chaining of operations. The component is implemented as combinational circuit and the steering logic existing inside the component allows to easily realizing any desirable complex hardware unit - called template - so that the data-path's performance benefits from the chaining of operations. Due to universal structure of the component, the synthesis of an application is accomplished by unsophisticated, yet efficient algorithms. An average reduction of 20% in latency is achieved when a comparison with a template-based data-path is performed. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ICECS.2004.1399726 | ICECS |
Keywords | DocType | Citations |
combinational circuits,data flow graphs,digital signal processing chips,logic design,DFG,DSP kernel acceleration,combinational circuit,data flow graph,flexible computational components,high performance data-path,latency reduction,operations inter-component chaining,operations intra-component chaining,steering logic,template complex hardware unit | Conference | 0 |
PageRank | References | Authors |
0.34 | 5 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michalis D. Galanis | 1 | 94 | 15.60 |
| George Theodoridis | 2 | 30 | 4.79 |
| Spyros Tragoudas | 3 | 625 | 88.87 |
| Dimitrios Soudris | 4 | 89 | 26.17 |
| Costas E Goutis | 5 | 186 | 25.76 |